TSMC has revealed the success of 3D IC packaging technology and is unveiling a new generation of semiconductor technology. At present, the industry believes that this technology is mainly to apply advanced processes below 5 nanometers, and pave the way for customized heterogeneous chips, and of course, further consolidate Apple orders.

The CoWoS architecture and integrated fan-out seal launched by TSMC in recent years were originally designed to explore the route of the post-Moore's Law era through the chip stack, and the emergence of real 3D packaging technology has further strengthened the competitiveness of TSMC's vertically integrated services. In particular, the future integration of heterogeneous chips will be a trend, integrating processors, data chips, high-frequency memory, CMOS image sensors and MEMS.

TSMC stressed that CoWoS and the integrated fan out package (InFO) are still 2.5D IC packages, and in order to make the chip more efficient, the chip industry has spent a considerable amount of time developing smaller, more complex 3D ics, which need to be combined with more difficult silicon drilling (TSV) technology. Wafer thinning, conductive material filling, wafer connection and heat dissipation support.

Packaging chips of different processes will be a big market demand, and the series of semiconductor supply chains is imperative. Therefore, so that TSMC is also actively invested in back-end semiconductor packaging technology, it is expected that ASE, SPIL and other sealing and testing factories will also accelerate the construction of 3DIC packaging technology and capacity. However, this is not an easy technology, and it needs to be paired with more difficult processes, such as silicon drilling technology, wafer thinning, conductive material filling, wafer connection and heat dissipation support, which will enter the new technical capital competition.

TSMC President Wei Che-jia said that although the semiconductor is in the off-season, but optimistic about the strong demand in the high-performance computing sector, and TSMC customer portfolio will become diversified. However, at present, TSMC's main kinetic energy still comes from the 7-nanometer process, and the trial production of 6-nanometer will begin in 2020, and advanced technologies such as 3D packaging should be adopted by only a few customers, and the industry suspects that Apple's mobile phone processor should still be the first order to introduce the latest process. Further news will not be announced until the TSMC Conference in May.